Preeminent Buffer Insertion Technique For Long Advanced On-Chip Graphene Interconnects

摘要

Graphene has become as one of the prospective on-chip VLSI interconnect materials due to its several superior electrical and mechanical properties. Graphene derived multi-layer graphene nanoribbon (MLGNR) has been investigated as one of the aptly suited on-chip VLSI interconnects. Long on-chip MLGNR interconnects are prone to various non-ideal effects such as signal degradation and crosstalk. The performance of the system deteriorates significantly as the length of interconnect increases. To mitigate this graving issue, novel buffer insertion technique for on-chip long MLGNR interconnects has been systematically presented and analyzed in the current paper. The practical CMOS driver-MLGNR interconnect-load model has been considered for analysis. The different analyses have been performed at 22nm technology node.