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EFFECT OF PACKAGE WARPAGE AND COMPOSITE CTE ON FAILURE MODES IN BOARD-LEVEL THERMAL CYCLING

机译:包装翘曲和复合CTE对板级热循环失效模式的影响

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Increasingly, demonstrating adequate reliability performance for a given packaged integrated circuit (IC) while mounted to a printed circuit board (PCB) that represents as closely as possible the final application is a requirement from both IC suppliers themselves and their Tier 1 customers. This combined with the ongoing miniaturization of electronic packages in both footprint and height, sometimes to the detriment of board-level reliability (BLR) thermal cycling (TC) performance, has put more scrutiny on the robustness of the interconnection from the package to the PCB. Well known byproducts of miniaturization that can lead to decreased solder joint interconnect fatigue lifetimes in BLR TC on BGAs, for example, include finer pitches with smaller solder spheres, larger die to package ratios and thinner laminate substrates. Not only is the fatigue lifetime in BLR TC examined closely, but also the specific failure modes and location. Additionally, depopulation of certain BGA locations to facilitate package substrate or PCB routing can affect BLR cycles to failure and influence the location of first failure. This paper will give examples of the BLR TC failure modes and locations of various package test vehicles that were designed to attempt to correlate those failure modes to the in plane CTE and out of plane warpage behavior of those packages. BLR TC results will be presented in Weibull format along with failure analysis using both cross-sectioning and dye penetrant analysis. Package CTEs were measured using Digital Image Correlation (DIC) and package warpage over approximately the same temperature range as TC was measured using CoolMoire, a Shadow Moire technique that brings the sample to temperatures as low as -55°C. The results show that by knowing both the warpage and CTE behavior of packages, the board mounted TC failure location, and to lesser extent, the relative performance, can be better understood. The two package types that will be studied are flip chip PBGA (FC PBGAs) and overmolded, wire-bonded PBGAs with various die sizes.
机译:越来越多地,在安装到印刷电路板(PCB)的同时表明适用于给定的封装集成电路(IC)的可靠性性能,该电路板(PCB)尽可能地遵循最终应用程序,这是两个IC供应商本身和他们的第一款客户的要求。这与电子封装的持续小型化相结合,占地面积和高度,有时会损害板级可靠性(BLR)热循环(TC)性能,对从包装到PCB互连的稳健性进行了更严格的审查。众所周知的小型化的副产品可以导致BGA的BLR TC中的焊接接头互连疲劳寿命减少,例如,具有较小的焊球,较大的模具与封装比和较薄的层压基板。不仅是BLR TC中的疲劳寿命密切检查,还有特定的故障模式和位置​​。另外,某些BGA位置以促进封装衬底或PCB路由的缺点可以影响BLR循环到故障并影响第一故障的位置。本文将赋予BLR TC故障模式和各种封装试验车辆的位置的示例,这些封装试验车辆旨在试图将这些故障模式与那些包装的平面CTE相关联以及超出这些包装的平面翘曲行为。 BLR TC结果将以Weibull格式呈现,以及使用横截面和染料渗透分析的故障分析。使用数字图像相关(DIC)测量包装CTE,并且使用COOLMOIRE测量TC的封装翘曲与TC相同的温度范围,将样品带到低至-55°C的温度。结果表明,通过了解套装的翘曲和CTE行为,电路板安装了TC故障位置,并且在较小程度上,相对性能可以更好地理解。将研究的两种包装类型是倒装芯片PBGA(FC PBGA)和具有各种模具尺寸的超模的引线PBGA。

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