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A New Process and Tool for Metal/High-K Gate Dielectric Stack for sub-45nm CMOS Manufacturing

机译:用于子45nm CMOS制造的金属/高k栅极介质堆的新工具

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In this paper we report the results of a new process and tool to deposit metal/high-k gate dielectric stack. Hafnium Oxide dielectric of 0.39nm EOT is deposited using Monolayer photo-assisted deposition process on a home-built system to provide a reliable and robust process to tackle the needs of the future CMOS generations. We report the results of 0.39nm EOT gate dielectric material with a leakage current density value of about 1×10{sup}(-12)A/cm{sup}2 for gate voltage from +3V to -3V. The data presented in this paper demonstrate that the process is robust and manufacturing tools can be developed without any fundamental barrier.
机译:在本文中,我们报告了沉积金属/高k栅极介电堆的新工艺和工具的结果。在家庭系统上使用单层照片辅助沉积工艺沉积0.39nm eot的氧化铪电介质,以提供可靠且坚固的过程来解决未来CMOS代的需求。我们将0.39nm EOT栅极介电材料的结果报告,漏电流密度值为约1×10 {sup}( - 12)a / cm {sup} 2,用于栅极电压从+ 3v到-3v。本文提出的数据表明,该过程是坚固的,并且可以在没有任何基础屏障的情况下开发制造工具。

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