The CD SEM (Critical Dimension Scanning Electron Microscope) is one of the main tools used to estimate Critical Dimension (CD) in semiconductor manufacturing nowadays, but, as all metrology tools, it will face considerable challenges to keep up with the requirements of the future technology nodes. The root causes of these challenges are not uniquely related to the shrinking CD values, as one might expect, but to the increase in complexity of the devices in terms of morphology and chemical composition as well. In fact, complicated three-dimensional device architectures, high aspect ratio features, and wide variety of materials are some of the unavoidable characteristics of the future metrology nodes. This means that, beside an improvement in resolution, it is critical to develop a CD SEM metrology capable of satisfying the specific needs of the devices of the nodes to come, needs that sometimes will have to be addressed through dramatic changes in approach with respect to traditional CD SEM metrology. In this paper, we report on the development of advanced CD SEM metrology at imec on a variety of device platform and processes, for both logic and memories. We discuss newly developed approaches for standard, III-V, and germanium FinFETs (Fin Field Effect Transistors), for lateral and vertical nanowires (NW), 3D NAND (three-dimensional NAND), STT-MRAM (Spin Transfer Magnetic Torque Random-Access Memory), and ReRAM (Resistive Random Access Memory). Applications for both front-end of line (FEOL) and back-end of line (BEOL) are developed. In terms of process, S/D Epi (Source Drain Epitaxy), SAQP (Self-Aligned Quadruple Patterning), DSA (Dynamic Self-Assembly), and EUVL (Extreme Ultraviolet Lithography) have been used. The work reported here has been performed on Hitachi CG5000, CG6300, and CV5000. In terms of logic, we discuss here the S/D epi defect classification, the metrology optimization for STI (Shallow Trench Isolation) Ge FinFETs, the detectivity of III-V STI FinFETs,, metrology for vertical and horizontal NWs. With respect to memory, we discuss a STT-RAM statistical CD analysis and its comparison to electrical performance, ReRAM metrology for VMCO (Vacancy-modulated conductive oxide) with comparison with electrical performance, 3D NAND ONO (Oxide Nitride Oxide) thickness measurements. In addition, we report on 3D morphological reconstruction using CD SEM in conjunction with FIB (Focused Ion Beam), on optimized BKM (Best Known Methods) development methodologies, and on CD SEM overlay. The large variety of results reported here gives a clear overview of the creative effort put in place to ensure that the critical potential of CD SEM metrology tools is fully enabled for the 5nm node and beyond.
展开▼
机译：CD SEM（临界尺寸扫描电子显微镜）是用于估计日期制造中的关键尺寸（CD）的主要工具之一，但作为所有计量工具，它将面临相当大的挑战，以跟上未来的要求技术节点。这些挑战的根本原因与缩小CD值没有唯一相关，因为可能期望的，但在形态和化学成分方面也是由于设备的复杂性的增加。实际上，复杂的三维设备架构，高纵横比特征和各种材料是未来计量节点的一些不可避免的特征。这意味着除了改进分辨率之外，开发能够满足节点设备的特定需求的CD SEM计量是至关重要的，需要通过关于方法的方法的巨大变化来解决。传统的CD SEM Metrology。在本文中，我们报告了IMEC在各种设备平台和流程上的高级CD SEM Metrology的发展，适用于逻辑和记忆。我们讨论标准，III-V和锗FINFET（FIN场效应晶体管）的新开发的方法，用于横向和垂直纳米线（NW），3D NAND（三维NAND），STT-MRAM（旋转转移磁力扭矩随机）访问内存）和RERAM（电阻随机存取存储器）。开发了线路（FEOL）和后端（BEOL）的前端的应用。就工艺而言，已经使用S / D EPI（源漏极外延），SAQP（自对准四分类图案化），DSA（动态自组装）和EUV1（极端紫外线图）。这里报告的工作已经在Hitachi CG5000，CG6300和CV5000上进行。在逻辑方面，我们在此讨论S / D EPI缺陷分类，STI（浅沟槽隔离）GE FINFET的计量优化，III-V STI FinFET的检测率，垂直和水平NWS的计量。关于记忆，我们讨论了STT-RAM统计CD分析及其与电气性能的比较，VMCO（空位调制导电氧化物）的电气性能与电气性能的比较，3D NAND ONO（氧化物氮化物氧化物）厚度测量。此外，我们还报告了CD SEM与FIB（聚焦离子束），优化的BKM（最佳已知方法）开发方法以及CD SEM覆盖层一起报告3D形态重建。此处报告的各种结果明确概述了所建立的创造性努力，以确保为5NM节点及更大的完全启用CD SEM Metrology Tools的临界潜力。
展开▼
