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HDL implementation of high performance 16 bit processor on FPGA

机译:FPGA上高性能16位处理器的HDL实现

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摘要

In this work a general purpose 16 bit processor is designed and simulated on two 28nm technology based FPGA's i.e. Atrix 7 and Kintex 7. Xilinx 14.2 has been used as the design tool. Major functional blocks of the processor i.e. ALU (arithmetic and logical unit), Register, Control Unit, Decoder and PC (program counter) unit are separately designed. It has a 5 stage pipeline to increase the speed of the processor. These modules are combined and tested using the Vivado Simulator of the Xilinx 2014.2. The outputs of the two devices are compared on the power and delay. The results show that while Kintex-7 is faster in terms of both maximum delay and clock skew, it has higher power dissipation as compared to Atrix-7 FPGA.
机译:在这项工作中,在两个基于28nm技术的FPGA(即Atrix 7和Kintex 7)上设计并仿真了一个通用的16位处理器。赛灵思14.2已被用作设计工具。处理器的主要功能模块,即ALU(算术和逻辑单元),寄存器,控制单元,解码器和PC(程序计数器)单元是分开设计的。它具有5级流水线,以提高处理器的速度。使用Xilinx 2014.2。的Vivado Simulator组合并测试了这些模块。比较两个设备的输出的功率和延迟。结果表明,虽然Kintex-7在最大延迟和时钟偏斜方面都更快,但与Atrix-7 FPGA相比,它具有更高的功耗。

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