A design for high speed leading-zero counter

摘要

Leading-zero counter (LZC) is a basic component in floating point operation. This paper aims at speeding up the operation of LZC. Based on new derived Boolean functions and complex logic gates, 8-bit LZC circuit is accomplished. Moreover, 16-bit LZC architecture is implemented in Xilinx field-programmable gate array (FPGA) and 32-bit LZC structure is realized on the platform of Application Specific Integrated Circuit (ASIC) in 65nm technology. Synthesis results are obtained on their special platforms. By comparison, our proposed design is faster than the reported designs.