Twin gate Tunnel FET based capacitorless dynamic memory

摘要

The work presents insights into operation, design and optimization of twin gate Tunnel Field Effect Transistor (TFET) for dynamic memory. The architecture utilizes two front gates, with the first gate aligned to source and responsible for read mechanism based on Band-to-Band Tunneling (BTBT), while the second gate regulates the creation and maintenance of dedicated volume for charge storage. The twin gate based dynamic memory at optimized bias values exhibits enhanced retention time of 370 ms at 85 °C and 1.3 s at 27 °C for gate lengths of 100 nm with better scalability, reliable operation at higher temperatures, and reduced write time of 5 ns.