A million wafer, virtual fabrication approach to determine process capability requirements for an industry-standard 5nm BEOL two-level metal flow

摘要

Process simulations provide vital insights to identify the key process steps to dedicate wafer resources for improvement or to determine investment on tool capability. We considered this problem in the context of an industry-like 5nm Back-End-of-Line flow being developed in IMEC and modeled the approximately 150 step process flow in COVENTOR SEMulator3D®. For the first time a one-million wafer Design of Experiments was conducted to sample a 10-dimensional variable space and derive the failure points for each process parameter. A vector based algorithm was used to search the parameter space and derive a hyper-surface to represent the absolute yield limits. The virtual wafers were run to identify process sensitivities and spec limits for expected process variations. This work highlights that process optimization is needed to improve the capability of many processes to the order of 1nm and this methodology should be used to screen standard libraries for process sensitivities.