A 8.0Gb/s source-series-terminated transmitter driver with 3 tap FFE for multi-standard applications in 65 nm CMOS

摘要

The paper designed a power-efficient and low-cost source-series-terminated (SST) driver with 3 tap feed forward equalization (FFE) for Peripheral Component Interconnect Express (PCIe3.0), RapidIO1.3 and XAUI applications in 65nm CMOS. The proposed SST structure adopted 3 kinds of resistance slice rather than single-2.4Kohm, 1.2Kohm and 600ohm to achieve a good compromise between area, power, and impedance adjustment and compensation range design. The improved novel topology can independently control impedance adjustment and equalization. Driver output impedance is adjustable from 43 to 62 ohms and can compensate up to -8.25dB. The power dissipation efficiency is 2.85mW/ (Gb/s) at a nominal supply voltage of 1.2V in full rate.