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Heterostructure at CMOS source/drain: Contributor or alleviator to the high access resistance problem?

机译:CMOS源/漏处的异质结构:是导致高访问电阻问题的原因还是缓解方法?

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This work investigates the interface resistivity of several heterostructures. Theoretical simulations suggest that, apart from the doping impact, the band offset and the difference in density of states (DOS) increase significantly the heterostructure interface resistivity. This conclusion corresponds well to our experiments that 1) high interface resistances are observed between (high-Ge content) p-SiGe/p-Si, n-InAs-Si, and n-InAs-Ge; and that 2) a TiSix/12nm Si:P-Ge contact with favorable band alignment between Si:P-Ge approaches low effective contact resistivity of 1.4×10-8 Ω cm2, close to a record-low value for n-Ge contacts.
机译:这项工作研究了几种异质结构的界面电阻率。理论仿真表明,除了掺杂影响之外,带偏移和状态密度(DOS)的差异也显着增加了异质结构界面的电阻率。这一结论与我们的实验非常吻合:1)在(高Ge含量)p-SiGe / p-Si,n-InAs / n-Si和n-InAs / n-Ge之间观察到高界面电阻; 2)在Si:P / n-Ge之间具有良好能带排列的TiSix / 12nm Si:P / n-Ge接触层接近1.4×10-8Ωcm2的低有效接触电阻率,接近于n-Ge接触。

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