Introduction

摘要

The semiconductor industry has relentlessly marched down a path which has enabled device dimensions with half pitches as small as 15nm to be realized. Spacer multiple patterning in particular has been invaluable for the NAND Flash market and, in recent years, has found its way into both DRAM and logic based devices. Spacer patterning has not only introduced additional processing costs, but also enabled scaling greater than the tradition 0.7 factor, with multiple device makers continuing to report lower cost per function.