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CHALLENGES OF SMT ASSEMBLY OF POP PACKAGES

机译:POP包装的SMT组装挑战

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The handheld market segment for mobile phones and tablets is driven by increasing multifunctional capabilities while continuously reducing form factors. To enable these next generation technologies, microelectronic packaging has evolved to include package-on-package (PoP) architectures where a memory package is stacked on top of an integrated architecture logic package. Today, one of most popular PoP designs for enabling small form factors involves attaching a memory to a logic device via through mold interconnects (TMI). The TMI stack-up brings a new set of challenges for surface mount (SMT) assembly in comparison to traditional interposer-based PoP configurations. This paper describes unique assembly challenges for TMI-based PoP packages and offers solution paths for improving SMT yield for memory attach. It discusses the impact of interactions between warpage shapes of logic and memory devices and effect of package geometric factor such as mold thickness on TMI failure modes. In addition to PoP geometry, SMT process parameters and assembly materials play a significant role in solder joint failure rates. Optimizing flux dip and transfer efficiency through SMT process can minimize defect rates, but without proper selection of material candidates successful SMT assembly is still in jeopardy. To improve memory assembly yield, flux materials with high tackiness and activity toward Sn/SnO need to be utilized. This study will review key materials characterization methods and materials properties to facilitate proper selection of solder flux materials benefitting the overall assembly yield of TMI PoP components. The disadvantages of choosing a dippable paste for memory package attach process will be discussed. Further, the explanation for why TMI PoP design requires a greater quantity of flux than interposer-based PoP architecture design for formation of defect-free TMI joints will be expounded and the industry's first TMI balls pre-coat technology as the solution for this need will be provided.
机译:手机和平板电脑的手持式市场领域是由不断增加的多功能功能同时不断减小外形尺寸推动的。为了实现这些下一代技术,微电子封装已经发展为包括堆叠式封装(PoP)架构,其中存储封装堆叠在集成架构逻辑封装之上。如今,用于实现小尺寸外形的最受欢迎的PoP设计之一涉及通过模制互连(TMI)将存储器连接到逻辑设备。与传统的基于中介层的PoP配置相比,TMI堆叠为表面贴装(SMT)组装带来了新的挑战。本文介绍了基于TMI的PoP封装所面临的独特组装挑战,并提供了解决方案途径,以提高内存附加的SMT成品率。它讨论了逻辑和存储设备的翘曲形状之间的相互作用以及封装几何因素(如模具厚度)对TMI失效模式的影响。除了PoP几何形状外,SMT工艺参数和组装材料在焊点故障率中也起着重要作用。通过SMT工艺优化助焊剂浸入和转移效率可以最大程度地降低缺陷率,但是如果没有正确选择候选材料,成功的SMT组装仍将面临危险。为了提高存储器组装的成品率,需要使用对Sn / SnO具有高粘性和活性的助焊剂材料。这项研究将回顾关键的材料表征方法和材料特性,以帮助正确选择助焊剂材料,从而有益于TMI PoP组件的整体组装良率。将讨论为存储器封装的附着过程选择可浸膏的缺点。此外,将解释为什么TMI PoP设计比基于中介层的PoP架构设计需要更多的助焊剂以形成无缺陷的TMI接头,并且行业首创的TMI球预涂技术将作为解决此问题的解决方案。提供。

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