Design of compact reversible online testable ripple carry adder

摘要

In this paper, we have presented an online testable full adder and an online testable n-bit ripple carry adder. To construct the compact online testable full adder as well as an online testable ripple carry adder, we have proposed a parity preserving adder gate namely CFTFA gate that optimizes the total numbers of gates, garbage outputs, quantum cost and constant inputs of the circuitry. We show that, the proposed designs are much better than the existing approaches considering all the efficiency parameters of reversible logic design. The proposed reversible online testable full adder using CFTFA gate achieves the improvement of 25% on the number of gates, 42.30% on quantum cost and 50% on the number of constant inputs over the existing best one. Several lemmas and an algorithm are presented to show the correctness of our proposed method.