EITHER-OR DATA SELECTOR, FULL ADDER, AND RIPPLE CARRY ADDER

摘要

Provided are an either-or data selector, a full adder, and a ripple carry adder. The either-or data selector comprises: a NOR logic circuit (XNR2), configured to receive a selection signal (sel) and an inverted first input (a0_n) and generate an intermediate result (gn1); and an AOI logic circuit (AOI21), configured to receive the selection signal (sel), a second input (a1), and the intermediate result (gn1) of the NOR logic circuit, and generate an inverted output (XN). The full adder comprises: an NAND logic circuit (ND2), configured to receive a first input (A) and a second input (B) and generate a first intermediate result (GN1); an OAI logic circuit (OAI21), configured to receive the first input (A), the second input (B), and the first intermediate result (GN1) of the NAND logic circuit, and generate a second intermediate result (TN1); a first NOR logic circuit (NR2), configured to receive the second intermediate result (TN1) of the OAI logic circuit (OAI21) and a third input (Cin_n) and generate a third intermediate result (GN2); an AOI logic circuit (AOI21), configured to receive the second intermediate result (TN1) of the OAI logic circuit (OAI21), the third input (Cin_n), and the third intermediate result (GN2) of the first NOR logic circuit (NR2), and to generate a first output (SUM); and a carry generation circuit (NP2B), configured to receive the first intermediate result (GN1) of the NAND logic circuit (ND2) and the third intermediate result (GN2) of the first NOR logic circuit (NR2) and generate a second output (Count_n).