Efficiency optimized 60 GHz CMOS Power amplifier for high PAPR signals

摘要

In this paper, a 60 GHz power amplifier is presented in 65nm CMOS technology based on the transformerless load-modulated (TLLM) amplifier architecture. It is designed to obtain high efficiency at output power back-off. The amplifier has 12.5 dB small signal gain and 11.5 dBm saturated output power. Measurement results show that this amplifier has more than 8% drain efficiency (7% power-added efficiency) in the last 6 dB output power range.