Improved logic synthesis for memristive stateful logic using multi-memristor implication

摘要

This paper presents two contributions to logic synthesis for memristive stateful logic. Firstly, we demonstrate the necessity to correct results provided by existing logic synthesis methods to ensure the expected computation. Secondly, we propose the concept of multi-memristor implication as a generalization of multi-input implication. Experimental results have shown a reduction of 6.5% in the number of operations when compared to previous works.