Combinational Logic Synthesis Research Report for Advanced Logic Synthesis forLow Power Mobile Applications Project

摘要

Timed Shannon Circuits have been proposed as a low-power circuit design style 1with the attractive properties of providing predictable, delay-insensitive low-power dissipation. In this report, we present the results of a comprehensive evaluation to compare the designs generated using Timed Shannon Circuits versus those generated by a commercial logic synthesis program (Synergy).