15.6 12b 250MS/S pipelined ADC with virtual ground reference buffers

摘要

High-performance op-amps in a switched-capacitor pipelined ADC consume high power to meet accuracy and speed requirements. This is aggravated by the decrease in intrinsic transistor gain and voltage headroom in nanoscale CMOS. Developments in pipelined ADCs have taken many unique directions to address these issues. Digital calibration of nonlinearity has enabled the use of low-performance op-amps. Non-op-amp-based approaches, such as zero-crossing-based circuits (ZCBC), the pulsed bucket brigade (PBB), and the ring amplifier (RA), have also been explored. This work presents a virtual ground reference buffer approach to significantly relax key op-amp specifications including unity-gain bandwidth, noise, and open-loop gain. Since the op-amp is allowed to settle fully, calibration to remove charge-transfer error in PBB and low gain or non-settling op-amp-based circuits is unnecessary. Also the transient current and corresponding voltage drop across switches and reference buffers in the ZCBCs and in non-settling op-amp-based circuits are avoided. The circuit is also shown to achieve higher maximum operating speed than alternative methods.