integrated circuit design; integrated circuit testing; system-on-chip; three-dimensional integrated circuits; SOC; TAM; TSV; bi-partitioning; core-based 3-D integrated circuits; embedded cores; system-on-a-chip; test access mechanism; three dimensional stacked integrated circuits; through silicon vias; Algorithm design and analysis; Partitioning algorithms; System-on-chip; Testing; Three-dimensional displays; Through-silicon vias;
机译:基于内核的片上系统集成电路的热安全测试计划
机译:基于内核的片上系统的集成LFSR重播,测试访问优化和测试计划
机译:基于专用测试层和测试计划的单片3-D集成电路测试设计解决方案
机译:通过双分区技术优化基于核的三维集成电路的测试时间
机译:用于优化模拟/ RF集成电路的数字辅助设计,仿真和测试技术。
机译:介电谱检测3-D集成电路中的早期故障
机译:功率约束下基于核的集成电路的测试计划