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TEST MODE ISOLATION AND POWER REDUCTION IN EMBEDDED CORE-BASED DIGITAL SYSTEMS OF INTEGRATED CIRCUITS (ICS) WITH MULTIPLE POWER DOMAINS
TEST MODE ISOLATION AND POWER REDUCTION IN EMBEDDED CORE-BASED DIGITAL SYSTEMS OF INTEGRATED CIRCUITS (ICS) WITH MULTIPLE POWER DOMAINS
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机译:具有多个功率域的集成电路(ICS)嵌入式基于核的数字系统中的测试模式隔离和功率降低
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摘要
Embodiments include a power isolation circuit. The power isolation circuit includes a logic block, a wrapper cell, an isolation cell, a test control unit, and/or a power control unit. The power control unit is coupled to the isolation cell and configured to receive a DFT internal core test mode control signal and a clamp control signal, and control the isolation cell dependent on the DFT internal core test mode control signal and the clamp control signal. Also disclosed is a multi-power domain multi-power isolation system, which includes a first power domain and a second power domain. The first power domain includes a logic block, wrapper cells, isolation cells, and a power control unit. The second power domain includes a logic block, wrapper cells, and level-shifter cells. The power control unit is coupled to the isolation cells. Additional power domains with similar characteristics can be included in the design.
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