An 8-bit 35-MS/s successive approximation register ADC

摘要

An 8-bit 35-MS/s successive approximation register analog-to-digital converter implemented in 0.18??m CMOS process is presented in this paper. To reduce the total power consumption, split capacitor DAC structure coupled with Merged Capacitor Switching (MCS) technique is used. In addition, dynamic comparator without pre-amplifier is applied to improve the energy efficiency. With the supply voltage of 1.8V and sampling rate of 35-MS/s, the ADC consumes 0.65mw and achieves an effective number of bits (ENOB) of 7.15 bits.