VHDL PROTOTYPING OF A 5-STAGES PIPELINED RISC PROCESSOR FOR EDUCATIONAL PURPOSES

摘要

This paper describes the VHDL (Very High Speed IC Hardware Description Language) implementation of a complete 5-stages, 32-bit, pipelined MIPS (Microprocessor without Interlocked Pipeline Stages) processor with integer multiplication and division support. The processor design supports all the 50 integer instructions including 25 R-type, 9 J-type and 16 I-type instructions. At the beginning, the processor's complete design is divided into three units: the pipelined datapath unit, the pipelined control unit and the hazard unit which solves all the problems of data hazards and control hazards. Then a program that finds the factorial of number 6 is executed and results are discussed. The VHDL design of the complete pipelined MIPS processor is implemented by using (Xilinx ISE Design Suite 13.4) program and configured on Xilinx Spartan-3AN FPGA (Field Programmable Gate Array) starter kit.