We report the impact of device design parameters on the saturation voltages (V_(DSAT)) and thereby on analog performance of the Tunnel FETs (TFET). As the drain bias (V_(DS)) increases, the device initially enters a soft saturation and later into a deep saturation state, both at a constant difference between the gate-drain bias (V_(GD)). An increase in source (drain) doping decreases (increases) the soft saturation voltage. The short channel lengths degrade the saturation in the TFETs. Agate-drain underlap causes early onset of the saturation in TFETs, while, a reduction in the nanowire diameter delays the saturation. The output resistance (R_o), transconductance (g_m), and intrinsic gain (g_m×R_o) increase when the device enters in soft saturation and attain a maximum in the deep saturation state. Our work elucidates the physics behind above observations, and provides insights into the device design of the TFETs.
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