A 8.125–15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop

摘要

The paper describes a 8.125–15.625 Gbps medium-reach SerDes macro for use in a networking memory system. The SerDes employs a sub-sampling ring-oscillator phase-locked loop to obtain a large frequency range with low jitter performance. In addition, the transmitter uses a modified hybrid output driver and a multi-step duty-cycle corrector. The receiver uses a BER-based calibration loop to find the set of parameters that maximizes the receiver voltage margin. The transmitter output achieves 160fs RMS jitter and 10.9ps total jitter at 15.625 Gbps with 140fs duty-cycle distortion.