Simulation-based reliability evaluation for analog applications

摘要

In this paper we present a new technology to improve the reliability evaluation for analog circuits based on fault simulation. A fault simulation framework has been developed and applied to reliability prediction in practice. In contrast to traditional reliability prediction the evaluation is not based on the “serial system approach”, which is mostly too pessimistic. Instead, the new approach considers all types of redundant structures within the system, even hidden redundancy and fault tolerance. The reliability prediction is more accurate because it is based on fault simulation results and the quantitative assessment of tolerated faults. This also results in a detailed reliability model related to practical reliability prediction in early design stages. By EDA integration the practical relevance has been highlighted.