Electromigration analysis of full-chip integrated circuits with hydrostatic stress

摘要

Interconnect reliability requirements of advanced process nodes have eroded design margins, increasing susceptibility to electromigration. Elaborate design requirements are needed to compensate for the lack of suitable materials to protect against such effects. Traditional electronic design automation verification tools exhibit significant difficulty when trying to validate these rules. We introduce a design context-aware interconnect reliability solution for full-chip electromigration analysis that considers current density, Blech Effect, and nodal hydrostatic stress analysis for failure prediction.