Multiplication acceleration through quarter precision wallace tree multiplier

摘要

This paper proposes a novel fixed point multiplier architecture with data level parallelism. That is, the same multiplier hardware is used to perform multiple multiplications on different data paths. Here, we proposed a Wallace tree multiplier to perform more number of multiplications in parallel with fewer extra carry save stages than conventional multiplier. The proposed n-bit Wallace structure is used to perform four (n/2)×(n/2)-bit multiplications, two n×(n/2)-bit multiplications and one n × n-bit multiplication in parallel. The experimental results are showing the comparison between the conventional 32-bit Wallace tree multiplier with proposed 32-bit Wallace tree multiplier. The proposed system is having slightly higher depth than conventional multiplier due to 2 extra carry save stages to incorporate multiple multiplications in parallel, which is not possible in conventional Wallace tree multiplier.