We have developed a 3D-stacked image sensor chip composed of CMOS image sensor (CIS) layer, correlated double sampling circuit (CDS) layer, and analog-to-digital converter (ADC) array layer using the chip-based 3D heterogeneous integration.technology. Three kinds of chips, CIS chip, CDS chip, and ADC chip, which were fabricated by different technologies, are processed and stacked vertically to form a prototype 3D-stacked image sensor. Through-Si vias (TSVs) and metal micro-bumps are formed in chip-level before stacking. The fundamental characteristics are evaluated in the fabricated prototype 3D-stacked image sensor.
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