How Much Does Regularity Help FPGA Placement?

摘要

Placement plays a key role in determining FPGA circuit characteristics. Meanwhile, its long computation time is an important factor that makes the flexibility of FPGA computing much less competitive than software compiling. One observation is that there is an increasing need for designs with regularity. A particular example is systolic array-based neural network circuit design. In this work, FPGA placement exploiting design regularity is studied. For neural network designs with systolic arrays, our proposed regularity-aware approach achieves 2X to 28X speed up versus Versatile Place and Route (VPR) with limited circuit performance loss. At the same time, its solution quality is almost perfectly correlated with VPR and thus renders its role for early prototyping.