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Requirements for Time-to-Digital Converters in the context of digital-PLL based Frequency Synthesis and GSM Modulation

机译:数字转换器在基于数字-PLL基于PLL的频率合成和GSM调制的上下文中的要求

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A key issue in proceeding the digitization of Phase-Locked Loops (PLLs) is the realization of proper phase detectors in the digital domain. This paper presents simulative analysis of the properties and requirements for Time-to-Digital Converters (TDCs) used for phase comparison in digitized fractional-N modulators with two-point modulation. Effects due to quantization of the TDC on frequency synthesis as well as GSM modulation quality are considered, defining the realization requirements for a transmitter.
机译:继续锁相环(PLL)的数字化的关键问题是在数字域中实现适当的相位检测器。本文介绍了用于在数字化分数N调制器中相位比较的时间转换器(TDC)的性质和要求的模拟分析,其具有两点调制的数字化分数N调制器。考虑了TDC对频率合成的量化以及GSM调制质量的影响,定义了发射机的实现要求。

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