A 288fs RMS jitter versatile 8–12.4GHz wide-band Fractional-N synthesizer for SONET and SerDes communication standards in 40nm CMOS

摘要

This paper presents a wide-band analog Fractional-N clock synthesizer operating from 8 to 12.4GHz suited for data communication standards. The synthesizer generates a low noise clock with rms jitter of 288–460fs, yet maintains wide loop bandwidth from 1.5 to 4.3MHz. The design consumes 16.9mW from a 1V supply, while occupying an area of 0.39mm2 in a 40nm CMOS technology.