A 32-Gbps 4#x00D7;4 passive cross-point switch in 45-nm SOI CMOS

摘要

This paper presents a passive 4×4 cross-point switch in 45-nm SOI CMOS technology for LVDS systems with near-zero power consumption. The CMOS switch dimensions and layout structures are optimized using full-wave electromagnetic simulations for the highest 3-dB bandwidth in order to maximize the data-rate for digital signal transmission. Also, a novel series switch is used between the cells to enhance the bandwidth. The 4×4 switch matrix results in a measured 3-dB bandwidth of ∼20–25 GHz (depending on the path) and an isolation > 40 dB at 26.5 GHz. The group delay variation is < ±5 psec., and results in very low jitter as seen from eye measurements (< 1.3 psec). Good eye-openings are obtained at 26 Gbps and up to 31.5 Gbps. The design is readily scalable to an 8×8 cross-point switch matrix.