A modified circuit-level strategy to improve the speed/stability trade-off of low-dropout regulators is presented. The technique, called hybrid-cascode compensation, is applied to stabilize the regulation loop. When designed carefully, results prove the efficacy of this method in minimizing output settling time under various transient conditions. Equivalently, power consumption and/or die area can be minimized for the same settling time. Employing this technique, a 0.7V-10mA voltage regulator with a minimum line voltage of 1V has been designed in 90nm CMOS technology. With improved settling time, stability is guaranteed for load capacitors as low as 50pF. Power supply rejection is always better than -30dB for all frequencies.
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