Modeling of HKMG Stack Process Impact on Gate Leakage, SILC and PBTI

摘要

Gate stack process (pre-clean, IL, IL/HK interface, HK, post-HK Nitridation) impact on gate leakage, SILC and PBTI is analyzed. IL and HK thickness, channel/IL and IL/HK energy-barrier offsets impact on gate leakage and SILC response from generated bulk traps inside IL and HK is quantified. Time kinetics of generated IL and HK bulk traps for SILC, and IL/HK interface traps for PBTI are simulated by a generic Reaction-Diffusion-Drift (RDD) framework. Model is validated using measurements from differently processed HKMG stacks.