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Lowering the Environmental Impact Of High-κ/Metal Gate Stack Surface Preparation Processes

机译:降低高κ/金属栅堆叠表面制备工艺对环境的影响

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摘要

Hafnium based oxides and silicates are promising high-κ dielectrics to replace SiO₂ as gate material for state-of-the-art semiconductor devices. However, integrating these new high-κ materials into the existing complementary metal-oxide semiconductor (CMOS) process remains a challenge. One particular area of concern is the use of large amounts of HF during wet etching of hafnium based oxides and silicates. The patterning of thin films of these materials is accomplished by wet etching in HF solutions. The use of HF allows dissolution of hafnium as an anionic fluoride complex. Etch selectivity with respect to SiO₂ is achieved by appropriately diluting the solutions and using slightly elevated temperatures. From an ESH point of view, it would be beneficial to develop methods which would lower the use of HF. The first objective of this study is to find new chemistries and developments of new wet etch methods to reduce fluoride consumption during wet etching of hafnium based high-κ materials. Another related issue with major environmental impact is the usage of large amounts of rinsing water for removal of HF in post-etch cleaning step. Both of these require a better understanding of the HF interaction with the high-κ surface during the etching, cleaning, and rinsing processes. During the rinse, the cleaning chemical is removed from the wafers. Ensuring optimal resource usage and cycle time during the rinse requires a sound understanding and quantitative description of the transport effects that dominate the removal rate of the cleaning chemicals from the surfaces. Multiple processes, such as desorption and re-adsorption, diffusion, migration and convection, all factor into the removal rate of the cleaning chemical during the rinse. Any of these processes can be the removal rate limiting process, the bottleneck of the rinse. In fact, the process limiting the removal rate generally changes as the rinse progresses, offering the opportunity to save resources. The second objective of this study is to develop new rinse methods to reduce water and energy usage during rinsing and cleaning of hafnium based high-κ materials in single wafer-cleaning tools. It is necessary to have a metrology method which can study the effect of all process parameters that affect the rinsing by knowing surface concentration of contaminants in patterned hafnium based oxides and silicate wafers. This has been achieved by the introduction of a metrology method at The University of Arizona which monitors the transport of contaminant concentrations inside micro- and nano- structures. This is the only metrology which will be able to provide surface concentration of contaminants inside hafnium based oxides and silicate micro-structures while the rinsing process is taking place. The goal of this research is to study the effect of various process parameters on rinsing of patterned hafnium based oxides and silicate wafers, and modify a metrology method for end point detection.
机译:based基氧化物和硅酸盐有望成为高κ电介质,以取代SiO 2作为最先进的半导体器件的栅极材料。但是,将这些新的高κ材料集成到现有的互补金属氧化物半导体(CMOS)工艺中仍然是一个挑战。一个特别关注的领域是在wet基氧化物和硅酸盐的湿法蚀刻过程中使用大量的HF。这些材料薄膜的图案化是通过在HF溶液中进行湿蚀刻来完成的。 HF的使用允许ha作为阴离子氟化物络合物溶解。通过适当地稀释溶液并使用略微升高的温度来获得相对于SiO 2的蚀刻选择性。从ESH的角度来看,开发降低HF使用量的方法将是有益的。这项研究的第一个目标是找到新的化学方法和新的湿法刻蚀方法,以减少to基高κ材料湿法刻蚀过程中的氟化物消耗。与主要环境影响相关的另一个相关问题是在蚀刻后清洁步骤中使用大量冲洗水去除HF。两者都需要更好地了解在蚀刻,清洁和冲洗过程中HF与高κ表面的相互作用。在漂洗过程中,从晶片上去除了清洁化学品。要确保漂洗过程中最佳的资源使用和循环时间,需要对传输效果有一个良好的理解和定量描述,这些传输效果决定了清洁化学品从表面的去除率。多种过程,例如解吸和再吸附,扩散,迁移和对流,均会影响冲洗过程中清洁化学品的去除率。这些过程中的任何一个都可能是去除速率限制过程,即冲洗的瓶颈。实际上,限制去除率的过程通常会随着漂洗的进行而变化,从而提供了节省资源的机会。这项研究的第二个目标是开发新的漂洗方法,以减少在单晶片清洁工具中漂洗和清洁of基高κ材料时的水和能量消耗。必须有一种计量方法,通过了解图案化pattern基氧化物和硅酸盐晶片中污染物的表面浓度,可以研究影响漂洗的所有工艺参数的影响。这是通过在亚利桑那大学采用一种计量方法来实现的,该方法可以监测污染物在微结构和纳米结构内部的传输。这是唯一能够在进行冲洗过程时提供ha基氧化物和硅酸盐微结构内部污染物表面浓度的度量​​衡。这项研究的目的是研究各种工艺参数对图案化ha基氧化物和硅酸盐晶片冲洗的影响,并改进用于终点检测的计量方法。

著录项

  • 作者

    Zamani Davoud;

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  • 年度 2012
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  • 原文格式 PDF
  • 正文语种 en
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