Metal hard-mask based AIO etch challenges and solutions

摘要

Trench-first-metal-hard-mask (TFMHM) approach has been widely utilized for copper interconnect formation since 45nm CMOS technology node. In TFMHM process integration development, four major challenges have to be solved. The first is the gap-fill due to the small top trench CD and the introduction of metal hard mask; the second is to meet the electrical targets through lower capacitance, lower metal sheet resistance and lower via contact resistance; the third is to meet yield requirement that ensure no short, bridge and open in all the design rule allowed patterns, and eliminate all killer defects; the last is the reliability related issues including metal and via related TDDB, upstream EM and downstream EM. Coupled with the optimization of wet clean process and proper choice of metal hard mask, a smooth and tapered trench profile could be delivered and the gap-fill performance could be greatly improved. The optimization of barrier/seed process coupled with the desired trench profile, via bottom CD and via chamfer profile, the on-target electrical performance could be achieved. The via bottom CD and chamfer profile are also critical to interconnects and etch process parameter optimization is important for defect elimination. With partial SAV process optimization, via related TDDB issue is solved and trench related TDDB is also not a problem for the above gap-fill friendly trench profile. For EM, we found the downstream EM lifetime is improved by gap filling friendly process and proper copper line CD.