Advanced NAND flash memory requires higher cell density [1–2]. With the gate pitch critical dimension (CD) of NAND flash memory drops to sub-50nm or even lower, numerous process problems occur [3]. Poly gate etching, evolving CG and FG formation, as the dominator for the poly gate profile, confronts critical challenges as the line fluctuation known as wiggling, side wall bowing, depth micro-loading between dense-pattern and iso-pattern area and tapered profile, especially when the aspect-ratio (AR) goes up to 10∶1. In this work, several special schemes are applied to avoid CG poly side wall bowing profile and to reduce over 50% depth micro-loading of FG etching between two different areas. Based on the improved depth loading, the etching profile can be optimized by the adjustments of etching parameters. Additionally, the pattern wiggling, which can be judged by line edge roughness (LER) measurement, is reduced by the fine hard-mask (HM) profile resulting from the improved corresponding etching step condition to enhance the cell line robustness.
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