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Multi-bit Gray Code Counter Based on FPGA

机译:基于FPGA的多位格雷码计数器

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摘要

According to the characteristics of Gray code,a method of separate count is presented. The 32-bit Gray code counter is programmed with VHDL on the platform of Quartus 2,and the simulation waveforms are achieved. The results indicate that Gray code counter counts accurately in the case of high clock frequency and obviously eliminates the emergence ofglitch. Compared with the ordinary binary counter,it has high stability and flexibility. This method is a reference to Hesicrn of counter.
机译:根据格雷码的特点,提出了一种单独计数的方法。在Quartus 2平台上使用VHDL对32位格雷码计数器进行编程,并获得了仿真波形。结果表明,在高时钟频率的情况下,格雷码计数器可以准确计数,并且明显消除了毛刺的出现。与普通的二进制计数器相比,它具有很高的稳定性和灵活性。此方法是对counter的Hesicrn的引用。

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