首页> 外文会议>2011 IEEE Computer Society Annual Symposium on VLSI >Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC
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Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC

机译:并行流水线ADC的低功耗,高速互补输入折叠稳压Cascode OTA设计

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摘要

This paper presents a low-power, high speed complementary input folded regulated cascode operational transconductance amplifier (OTA) designed for the 10bit, 150MSPS parallel pipeline ADC. The OTA plays an important role in the ADC, because of its conversion rate and power consumption are limited by the performance of the OTA. The designed ADC in this paper employs parallel pipeline architecture based on double sampling sampled hold (DSSH) technique, and shares the OTA between two channels of the ADC. The folded cascode OTA consists of fully differential and regulated cascode gain boosting technique. Besides, a Common Mode Feed Back (CMFB) circuit was introduced and some methods are concerned to improve the performance. Then, by proper optimization of the layout design, OTA''s mismatch was reduced up-to a great extent. With 1.8V power supply, using the CMOS9T5V 180nm process technology, the simulation shows that the open-loop gain of the OTA is 90.39 dB, the phase margin (PM) is 63.85° with the unity gain bandwidth (UGB) of 700.7 MHz. The power consumption of this OTA is only 3.24 mW, which significantly reduces the whole power consumption of the parallel pipeline ADC.
机译:本文介绍了一种专为10bit,150MSPS并行流水线ADC设计的低功耗,高速互补输入折叠稳压共源共栅运算跨导放大器(OTA)。 OTA在ADC中起着重要作用,因为它的转换速率和功耗受OTA性能的限制。本文设计的ADC采用基于双采样采样保持(DSSH)技术的并行管线架构,并在ADC的两个通道之间共享OTA。折叠后的共源共栅OTA包括全差分和稳压共源共栅增益提升技术。此外,介绍了一种共模反馈(CMFB)电路,并提出了一些改善性能的方法。然后,通过适当优化布局设计,可以最大程度地减少OTA的不匹配。在使用1.8V电源的情况下,使用CMOS9T5V 180nm工艺技术,仿真显示,OTA的开环增益为90.39 dB,相位裕量(PM)为63.85°,单位增益带宽(UGB)为700.7 MHz。该OTA的功耗仅为3.24 mW,这大大降低了并行流水线ADC的整体功耗。

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