Design of on-chip Transient Voltage Suppressor in a silicon-based transceiver IC to meet IEC system-level ESD specification

摘要

The on-chip Transient Voltage Suppressor (TVS) embedded in the silicon based transceiver IC has been proposed in this paper by using 0.8 μm Bipolar-CMOS-DMOS (BCD) process. The structure of the on-chip TVS is a high voltage Dual Silicon-Controlled-Rectifier (DSCR) with ±19V of high holding voltage (Vh) under the evaluation of 100ns pulse width of the Transmission Line Pulsing (TLP) system. The holding current (Ih) of the on-chip TVS is so high that can pass ±200mA latchup testing. Therefore, the on-chip TVS can be safely applied to protect the ±12V of signal level for RS232. The RS232 transceiver IC with on-chip TVS has been evaluated to pass the IEC61000-4-2 contact ±12kV stress without any hard damages and latchup issue. Moreover, the RS232 transceiver IC also has been verified to well protect the system over the IEC61000-4-2 contact ±20kV stress (CLASS B) in the smart scanner and notebook application