An implementation method of Canny edge detection algorithm on FPGA

摘要

Canny algorithm is an excellent edge detection algorithm and is widely used in the field of image processing. But the usage of Canny algorithm on the embedded image processing platform has been restricted since it needs a large amount of computation. In this paper, a parallelized architecture of Canny algorithm and its implementation on FPGA are proposed based on the analysis of the computing procedure of Canny algorithm. Experimental results show that, both good performance and high processing speed of edge detection can be obtained using the method proposed in this paper.