Process Variability Modeling for VLSI Circuit Simulation

摘要

This paper presents a systematic methodology to develop statistical compact MOS models for advanced VLSI circuit simulation. Process variability in advanced CMOS technologies imposes a serious challenge for computer-aided VLSI circuit design. Therefore, statistical compact model has become indispensable for realistic assessment of the impact of random process variability on advanced VLSI circuit performance. This paper describes the major parameter set causing local and global process variability in nanoscale CMOS devices and presents a methodology to generate simplified statistical compact MOS models for VLSI circuit simulation.