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IN-LINE EVALUTION METHOD OF THE INTRINSIC STRESS OF THIN FILMS USED FOR TRANSISTOR STRUCTURES

机译:用于晶体管结构的薄膜的内在应力的在线评估方法

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Both thermal and intrinsic stresses that occur during thin-film processing and assembly processes dominate the final residual stress in thin film electronic devices. Since the residual stress causes the shift of electronic functions of dielectric and semiconductor materials, these shifts sometimes degrade their performance and reliability. Therefore, it is very important to measure and control the residual stress in thin-film-applied products. In this study, the changes of the electronic performance of MOS transistors by mechanical stress were measured by applying a four-point bending method.The stress sensitivity of the transconductance of NMOS transistors increased from about 1%/100-Mpa to about 15%/100-Mpa by decreasing the gate length of the transistors from 400 nm to 150 nm. One of the estimated important factors which dominated this increase was attributed to the interference of stress concentration fields occurred at the edges of gate-electrodes. The change of the residual stress in a transistor structure caused by deposition of thin films was analyzed by applying a finite element method (FEM).The estimated change was validated by experiment using originally developed stress sensing chips. The estimated change of the stress due to deposition of gate electrode tungsten film was about 25MPa. The measured average stress was about 20MPa and it agreed well with the estimated value. In addition, the change of the residual stress caused by the interference of the stress concentration fields between two gate-electrodes was validated by applying this stress sensing chip. The measured change of the stress caused by making fine slits by focused ion beam was about 70MPa and it agreed well with the estimated value of about 60MPa. It was confirmed, therefore, that both the thin film process-induced stress and the assembly-induced stress change the final residual stress in a transistor structure and the change can be evaluated by our stress-sensing chip quantitatively.
机译:在薄膜加工和组装过程中产生的热应力和固有应力均主导着薄膜电子设备中的最终残余应力。由于残余应力会导致电介质和半导体材料的电子功能发生偏移,因此这些偏移有时会降低其性能和可靠性。因此,测量和控制施加薄膜的产品中的残余应力非常重要。在这项研究中,通过应用四点弯曲法测量了由于机械应力而导致的MOS晶体管的电子性能变化。 通过将晶体管的栅极长度从400 nm减小到150 nm,NMOS晶体管的跨导的应力敏感性从大约1%/ 100-Mpa增加到大约15%/ 100-Mpa。主导这一增加的估计重要因素之一归因于在栅电极边缘发生的应力集中场的干扰。通过应用有限元方法(FEM)分析了由薄膜沉积引起的晶体管结构中残余应力的变化。 使用最初开发的应力感测芯片通过实验验证了估计的变化。估计的由于栅极钨膜沉积而引起的应力变化约为25MPa。测得的平均应力约为20MPa,与估计值非常吻合。另外,通过应用该应力感测芯片,验证了由两个栅电极之间的应力集中场的干扰引起的残余应力的变化。测得的聚焦离子束细缝造成的应力变化约为70MPa,与估计值约60MPa吻合得很好。因此,可以肯定的是,薄膜工艺引起的应力和组装引起的应力均会改变晶体管结构中的最终残余应力,并且该变化可以通过我们的应力感应芯片进行定量评估。

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