Continuous scaling of CMOS devices in nm regime along with the complex processes result in increasing stress contribution in circuit performance that is no longer second order effect. Shallow Trench Isolation (STI) induced mechanical stress impacts analog designs dramatically, it is sufficient to shift bias point, change design parameters, and cause severe mismatch between transistors. This paper presents a design methodology in order to avoid stress effects in analog/mixed signal designs. This methodology flow is based on early prediction of stress effects prior to layout design to save time and avoid further costly layout iterations. Impact of STI stress on circuit performance is characterized in 40-nm CMOS technology through an op-amp and a latched comparator circuits. Furthermore, the performance after applying the proposed methodology is shown for methodology verification.
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