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Module miniaturization by ultra thin package stacking

机译:超薄封装堆叠使模块小型化

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The scope of the European project TIPS (Thin Interconnected Package Stacks) is the fabrication of ultra thin packages for electronic components and the subsequent stacking and interconnection of those packages to form highly compact modules. In the first part of this paper approaches to fabricate ultra thin 10 × 10 mm packages by embedding technologies for chips into printed circuit board environments will be discussed. Technologies for commercial flexible printed circuit board substrates (polyimide sandwiched in Cu layers) and respective fabrication processes are used. After initial patterning of the Cu the chips are die bonded to the flex substrates and subsequently lamination into build up layers. Electrical contact between the chip and a fan out routing on the outer layer of the package are made by micro via formation, electroplating and wet chemical structuring of the metal layers. The thickness of the embedded components is constricted to 50 µm in order to constrain the package thicknesses to a maximum of 100 µm with this approach. Packages are fabricated in batches of 150 × 150 mm sheets of flex substrates. Stacking of individual packages can be performed in an automated package by package placement process using a frame as alignment tool and typical flexible printed circuit boards adhesives. In this way only known-good-packages are stacked in order to minimize yield loss. However, a more straight forward process is stacking of the packages using fabrication batches and established multilayer printed circuit board technologies. The disadvantage is the potential yield loss if one of the packages in a stacked layer is faulty. For either type of stacking process the individual stacks have to be milled out of the stack fabrication batch. After stacking and sound mechanical interconnection the electronic interconnection between layers is made by the sequence mechanical through hole drilling, plating and wet chemical structuring. Tes--t issues, design considerations and results of first fabrication runs will be presented and discussed.
机译:欧洲项目TIPS(薄互连封装栈)的范围是制造用于电子组件的超薄封装,以及随后将这些封装堆叠和互连以形成高度紧凑的模块。在本文的第一部分中,将讨论通过将芯片嵌入到印刷电路板环境中的技术来制造超薄10×10 mm封装的方法。使用用于商业柔性印刷电路板基板(夹在Cu层中的聚酰亚胺)的技术和相应的制造工艺。在对Cu进行初始构图后,将芯片模片粘合到柔性基板上,然后层压成堆积层。芯片与封装外层上的扇形布线之间的电接触是通过金属层的微通孔形成,电镀和湿化学结构化来实现的。嵌入式组件的厚度限制为50 µm,以便通过这种方法将封装厚度限制为最大100 µm。包装以150×150 mm的柔性基板分批制造。单个包装的堆叠可以使用框架作为对齐工具和典型的柔性印刷电路板粘合剂通过包装放置过程以自动包装的形式进行。以这种方式,仅堆叠已知良好的包装以最小化成品率损失。但是,更直接的方法是使用制造批次和已建立的多层印刷电路板技术来堆叠封装。缺点是,如果堆叠层中的其中一个封装出现故障,则可能会导致产量损失。对于任一类型的堆叠过程,必须将单个堆叠从堆叠制造批次中铣出。在堆叠和良好的机械互连之后,各层之间的电子互连是通过机械通孔钻孔,电镀和湿化学结构化的顺序进行的。特斯 -- 将介绍和讨论首次制造运行中的问题,设计注意事项和结果。

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