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Ultra-low power TFTs with 10 nm stacked gate insulator fabricated by nitric acid oxidation of Si (NAOS) method

机译:通过Si的硝酸氧化(NAOS)方法制造的具有10 nm堆叠栅绝缘体的超低功率TFT

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We have succeeded in fabrication of ultra-low power poly-Si based thin film transistors (TFTs) with 10 nm gate insulators and 1 V driving voltage. An ultrathin interfacial SiO2 layer formed in 68 wt% nitric acid (HNO3) aqueous solutions at 120°C decreases a gate leakage current by two orders of magnitude, resulting in a high on/off ratio of 109.
机译:我们已经成功地制造了具有10 nm栅极绝缘体和1 V驱动电压的基于超低功率多晶硅的薄膜晶体管(TFT)。在120°C下于68 wt%的硝酸(HNO 3 )水溶液中形成的超薄界面SiO 2 层将栅极泄漏电流降低了两个数量级,从而导致高开/关比10 9

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