A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias

摘要

We present a 0.5 V 6T SRAM fabricated in a 90 nm PD-SOI technology with asymmetric MOSFET to improve the read and write margin. The design also uses a forward-body-bias technique in the bit-cell and peripheral circuits. The measured minimum operating voltage of the SRAM is 0.45 V at 25°C, which is 100 mV lower than conventional SRAM. The access time is 6.8 ns at 0.5 V.