首页> 外文会议>Applied Superconductivity and Electromagnetic Devices, 2009. ASEMD 2009 >A new back-gate SOI high voltage device with a compound layer
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A new back-gate SOI high voltage device with a compound layer

机译:具有复合层的新型背栅SOI高压器件

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摘要

A back-gate silicon on insulator (SOI) high voltage device with a compound layer (BG CL SOI-LDMOS) is proposed to enhance breakdown voltage of SOI device. Introducing of compound layer(CL) can effectively suppress gain of surface electric field at source side, and increase electric field in the buried oxide layer. Thus breakdown voltage of device is increased remarkably with invariable specific on-resistance. The breakdown voltage and electric field profile are researched for the new structure by using 2D MEDICI software. Simulation result shows that BG CL SOI-LDMOS can reach 557 V, 165.8 % higher than conventional SOI, at 1μm-thick buried oxide layer, 40 μm-length drift region and 240V back-gate voltage.
机译:为了提高SOI器件的击穿电压,提出了一种具有复合层的背栅绝缘体上硅(SOI)高压器件(BG CL SOI-LDMOS)。引入化合物层(CL)可有效抑制源侧表面电场的增益,并增加掩埋氧化物层中的电场。因此,器件的击穿电压以不变的特定导通电阻显着增加。使用2D MEDICI软件研究了新结构的击穿电压和电场分布。仿真结果表明,在厚度为1μm的掩埋氧化物层,长度为40μm的漂移区和240V背栅电压下,BG CL SOI-LDMOS可以达到557 V,比常规SOI高165.8%。

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