EFFECTS OF HOT CARRIER STRESS ON RELIABILITY OF STRAINED-SI MOSFETS

摘要

Uniaxial tensile strained-Si NMOS and compressive strained-Si PMOS devices have been successfully integrated within a 90mn CMOS process technology [1], Strain in the MOS channel leads to mobility enhancements due to reorientation of the band structure induced by the strain. However, at the same time, the strain in the channel also leads to band-gap narrowing and an increase of the phonon mean free path [2], both of which are a concern for higher impact ionization. A competing effect from strain, however, is the increase in the channel/dielectric barrier that can reduce hot carrier injection [3]. Previously published results [4-6] have shown opposite trends for hot electron reliability in strained-Si MOSFETs. The focus of this work is to demonstrate the effect of mechanical stress in the channel on the impact ionization rate (IIR) and on hot carrier reliability for both NMOS and PMOS devices. In addition, this study will explain the reason for the wide disagreement between published reports on this behavior. It is shown for the first time that the IIR reaches a maximum value with strain for NMOS and then reduces as higher levels of strain are applied. Compressive strained PMOS devices do not show this peak in IIR.