Gate Edge Roughness in Electron Beam Direct Writeand its Influence to Device Characteristics

摘要

Line edge roughness (LER) and line width roughness (LWR) have raised questions and concerns as currentlithography techniques reduce critical dimensions (CD) below 50 nm. There are few applications of controlled variationof LER and LWR, even among those which use electron beam direct writing (EBDW), although it is highly desirable totest the influence of systematical variation of LER and LWR on actual semiconductor devices. To get a clearunderstanding how and what the LERs and LWRs are influencing in EBDW, we have designed and fabricated transistorgates with programmed LER and LWR using EBDW and observed those based on CD-SEM metrology. The obtainedresults including calculated power spectrum density (PSD) shows the capability of EBDW to control the LER/LWR.Further, the influence of edge/width roughness in EBDW on device characteristics is reviewed and it gives how theeffect of LWR/LER translates to device performance in DRAM process flow. It is found that the control of LWR is moreimportant than that of LER for future lithography developments.